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- Figure 1 from An Improved VLSI Architecture of S-box for AES Encryption | Semantic Scholar
- Figure 1 from An Improved VLSI Architecture of S-box for AES Encryption | Semantic Scholar
- Figure 3 from An Improved VLSI Architecture of S-box for AES Encryption | Semantic Scholar
- Table I from An Improved VLSI Architecture of S-box for AES Encryption | Semantic Scholar
- Table III from An Improved VLSI Architecture of S-box for AES Encryption | Semantic Scholar
- Table II from An Improved VLSI Architecture of S-box for AES Encryption | Semantic Scholar
- Table IV from An Improved VLSI Architecture of S-box for AES Encryption | Semantic Scholar
- Figure 2 from Low latency VLSI architecture of S-box for AES encryption | Semantic Scholar
- Figure 3 from Low latency VLSI architecture of S-box for AES encryption | Semantic Scholar
- Table I from Low latency VLSI architecture of S-box for AES encryption | Semantic Scholar