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 have demonstrated remarkable performance in automatically generating code for general-purpose programming languages like Python. However%2C these methods fail on hardware description languages (HDLs) like Verilog due to the scarcity of high-quality instruction tuning data%2C as even advanced LLMs like GPT-3.5 exhibit limited performance on Verilog generation. Regarding this issue%2C we observe that (1) Verilog code collected from the real world has higher quality than those generated by LLMs. (2) LLMs like GPT-3.5 excel in summarizing Verilog code rather than generating it. Based on these observations%2C this paper introduces CodeV%2C a series of open-source instruction-tuned Verilog generation LLMs. Instead of generating descriptions first and then getting the corresponding code from advanced LLMs%2C we prompt the LLM with Verilog code and let the LLM generate the corresponding natural language description by multi-level summarization. Experimental results show that CodeV relatively surpasses the previous open-source SOTA by 14.4%25 (BetterV in VerilogEval) and 11.3%25 (RTLCoder in RTLLM) respectively%2C and also relatively outperforms previous commercial SOTA GPT-4 by 22.1%25 in VerilogEval.?quality=80&w=800)
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