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Related Visuals
- An efficient synthesis method for ternary reversible logic | Semantic Scholar
- Figure 14 from A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | Semantic Scholar
- Figure 14 from A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | Semantic Scholar
- Figure 2 from Energy-Efficient CNTFET-RRAM Based Ternary Logic Design | Semantic Scholar
- Figure 2 from Energy-Efficient CNTFET-RRAM Based Ternary Logic Design | Semantic Scholar
- Figure 10 from A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | Semantic Scholar
- Figure 10 from A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | Semantic Scholar
- Figure 10 from A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | Semantic Scholar
- Figure 10 from A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | Semantic Scholar
- Figure 5 from Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates ...